Instructor Office Hours and TA Lab Hours
Course Email Archive
Lab Report Format
Quartus II Resources
Quartus II Web Edition Software Version 7.1 SP1 by Altera
MIDI-OX MIDI Utility
AVR Studio 4 by Atmel
College of Engineering
Department of Electrical and Computer Engineering
University of Massachusetts, Amherst
Department of Electrical and Computer Engineering
ECE 353 - Computer Systems Lab I - Fall 2012
Course web site: ece353.ecs.umass.edu (note change of class URL from last year)
Design and analysis of digital systems using
both hardware (Altera Complex Programmable Logic Device (CPLD) and
Verilog) and software (Atmel AVR ATmega32 microcontroller, assembly
language and C). The four labs will cover topics such as finite state
machines, C programming, models of CPUs and memory in C and Verilog, and
asynchronous and synchronous serial data communication. Emphasis will
be placed on sound engineering practices, including team-based hw/sw
development and time management, debug, demonstration and documentation.
Prerequisite: C or better in ECE 232
Lecture Times: Tue and Thu, 1:00PM - 2:15PM, Room: Ag. Engin. Bldg 119 - please check schedule for details for when each lab lecture is hold. Also check SPIRE.
- co-taught by Profs Krishna and Moritz
- Keith Shimeld - ECE Trailer, tel: 545-3523, firstname.lastname@example.org
Shop hours: M-F 8:30-11:30 AM and 1:00-3:30 PM, ECE Trailer, southeast
of the ELab I Building, north of the Gunness Lab.
Textbook: No official textbook is required for the course.
All handouts and course materials will be posted on the course web site
- see TA Lab hours link on the left
1. Describe, design, and verify digital hardware using the VERILOG
2. Use the C language to model digital components such as cache and
3. Implement digital hardware such as synchronous and asynchronous
serial interfaces using programmable logic as well as
4. Program a microcontroller (AVR) in both assembly and C language
5. Demonstrate hardware and software-based embedded systems using a
6. Work in a team, learning how to partition tasks and share
7. Learn to plan and manage time to get it done by a deadline
8. Document designs and the design process with formal written laboratory reports.
- Lab A - Cache Simulator (C)
- Lab B - Design of MIDI Receiver (Verilog)
- Lab C - Pipelined Machine (C)
- Lab D - IR Music Box (C &/or Assembly)
Each team will demonstrate the project to the instructor at a specified due time
and will submit a report for each lab.
Each team will be composed of up to Three (3) students including one team lead. The team lead is responsible for enforcing time management in the team. Each team member has to be familiar with all aspects of each project, but the team lead will need to make sure that the group starts that project in time and follows a schedule for how the work is completed.
The grade will consist of grade for Q&A during demos and reports for each lab and final exam. Class attendance is required.
Final Exam: 30%
Lab A: 11.67%
Lab B: 17.5%
Lab C: 23.33%
Lab D: 17.5%
Late submission of reports will attract a penalty of 20% per day.
Reports for Labs B and D must include a plan by the team lead showing how a lab was gradually completed with at least one intermediate milestone reached (show when) and whether team members followed/met the schedule put forward. Time management will be a key aspect graded in addition to a successful completion of the technical work.
Lab Demo, Report Schedule:
NO ASSIGNMENTS WILL BE ACCEPTED LATER THAN FIVE DAYS AFTER THE DEADLINE.
The course is composed of the Lecture section and the Lab section.
The lectures will provide a detailed introduction for each lab project, will introduce Quartus software, and present tutorials for Verilog HDL, AVR, and WinAVR.
We will issue software licenses of the Altera Quartus II and other tools for use on your personal computers at home so that you can perform most of the design and simulation work outside of the lab. The extended lab hours will be announced later.
Each group will be assigned a workbench drawer and a key for their kits, including
breadboard and parts. Logic analyzers and additional parts that you may need will be
signed out with the TA. You should not leave your breadboard or
parts unlocked in the lab; you will not receive a grade for
this course if the kits are not returned by the end of the semester.
You may take your breadboard and components out of the lab, but essential lab
equipment (oscilloscopes, logic analyzer probes, etc.) and manuals are NOT to leave the lab.
Please report any problems you encounter with lab equipment,
components, and breadboards to the TAs or the technician.
Don't try to fix the hardware, or just move to a different logic analyzer or stuff the bad component back into your kit and have other groups encounter the same problems as you. Please take the extra time to make sure that the equipment gets fixed or the bad
component gets identified.
Students take full financial responsibility for lab equipment signed out
to them and understand that failure to return that equipment by the due date
will result in a grade of Incomplete and possible administrative withdrawal.
It is absolutely required that you simulate your design before wiring it up, using Altera's Quartus II simulator and other software.
It is much easier to debug problems in your design through simulation than to try to find them in the prototype.
This way you will spend less time in the lab, in front of a logic analyzer
or oscilloscope, and more in front of a simulator on a PC at home or
in the PC lab. You are required to submit a logic, block or circuit diagram
(whichever appropriate) of your design with the report.
When a group demonstrates a working design, we expect all partners to fully
understand the design. Every member of a group is ``jointly and
severally'' responsible for their group's entire report and demonstration,
and is expected to have detailed knowledge of the entire lab, including
those parts implemented by other members of the group.
All partners may not necessarily receive the same grade if it becomes clear that one has done significantly more/less work than the other(s).
You should work as a team. If you are the more experienced
designer/debugger in the group, we expect you to provide some patience
and help to your partner(s). If you are the less experienced
designer/debugger, we expect you to work extra hard to learn.
Your report should include a thorough explanation of your design approach, with printed logic schematics, simulation results, and logic analyzer printouts.
Reports should be typed using word processor, and include figures and
schematics to illustrate your points.
In addition, you should include a description of any problems you
encountered during the debugging and how you resolved them.
The intention of the latter requirement is not to inform us how bad your
original design was or how hard you had to work to fix it,
but rather to get you into the habit of keeping track of debugging problems.
Finally, we expect all members to contribute equally to the project report,
even though only one project report is required from each group.
Keep the Lab Clean
Please keep your workplace clean and shut off all equipment
(logic analyzers, printers, PCs, etc.) when you are done working on it.
Please clean up wire strips, paper, etc., from your work area;
nobody else will do it for you.
Computer paper must be recycled, so please place it in the designated
bins outside the lab.
No Eating or Drinking in the Lab
Eating or Drinking in the lab is strictly prohibited.
Eating or drinking in the lab is not only inappropriate,
but may also cause contamination of the sensitive and expensive
equipment, eventually leading to its malfunctioning.
Any student caught violating this requirement will have the grade
for the respective project reduced to 0 (zero).
We encourage students to discuss the design and debugging problems
among the groups. However, there is a fine line between discussion of the
problem and discussion of the solution.
Each group must independently arrive at its own solution to each project.
Exchange of software code, truth tables, state or gate diagrams scribbled on paper,
partial or full schematics, parts of lab reports and the like is strictly forbidden and may result in your failing the course. We have access to code submitted by earlier students who took this course; as a result, we can use appropriate software tools to detect any attempt to copy from them.
21 August 2012, Updated by Prof C. Andras Moritz